The present invention relates to a logic circuit including a logic LSI such as a processor that has a resistance of soft errors at an active time and, more particularly, to a high-performance microprocessor having error detection logic.
A logic LSI having high-speed action can be realized by a dynamic logic circuit. The dynamic logic circuit determines the potential of an output signal by holding or discharging a charge, which is stored in a dynamic node by a precharge, in accordance with a logic function. As a result, no short current flows at the active time so that the dynamic logic circuit can act at a high speed.
However, the charge, as stored in the dynamic node, may be erroneously discharged by noise caused, for example, by the incidence of .alpha. rays. At such time, the result of the logic function cannot be correctly reflected in the output of the dynamic logic circuit thereby to cause an error. This type of error will occur not steadily but only with the occurrence of noise such as the incidence of .alpha. rays, so that it is called "soft error".
A technique for making the high-speed action possible while resisting the aforementioned soft error at a single gate level is disclosed in Japanese Patent Laid-Open No. 168724/1990 (hereinafter the "First Prior Art"). This technique is realized by noise suppression means for holding the charge of a dynamic node after the precharge action, and means for precharging the internal node of an n-MOS network constructing the logic function. If the noise suppression means for holding the charge of the dynamic node is strengthened, the soft error can be sufficiently suppressed. On the other hand, however, the short current at the logic action time is increased to obstruct the high-speed action. By precharging the internal node of the n-MOS network constructing the logic function, therefore, the noise is prevented from occurring due to the charge share, and the noise suppression means for holding the charge of the dynamic node suppresses only the noise due to the incidence of .alpha. rays. As a result, the strength of the noise suppression means can be reduced to a minimum necessary for suppressing the occurrence of noise due to the incidence of .alpha. rays, so that the short current at the logic action time can be reduced to allow a high-speed action at some level.
An example of attaining resistance to soft error not at the single gate level but for a logic block of considerable size is disclosed on pp. 54 to 55 of "1982 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS" (hereinafter the "Second Prior Art"). According to the disclosed method, an error is detected in data by adding parity to the data and detecting an error in a logic circuit by duplexing a logic circuit to compare its outputs. Thus, there is provided means for discriminating between normal and abnormal actions, not by suppressing the occurrence of a noise due to the incidence of .alpha. rays, but by detecting the soft error due to noise directly.
A method of constructing a logic circuit having an effect similar to that of duplex logic circuits is disclosed on pg. 21 of "1996 IEEE International Solid-State Circuits Conference TUTORIAL#4" (hereinafter the "Third Prior Art"). The dynamic logic circuit forming the single gate is a circuit for generating both a true output and a complement output. Because of the dynamic circuit, both the output signals take a low potential at the precharge time, and one of the output signals is changed to a high potential at the logic action time. Since both the output signals intrinsically never take high potential at the same time, the error can be detected if both the output signals should simultaneously take the high potential.